Memory Controller IP Core for DDR2 SDRAM

Block Diagram
Overview
Features
Data Sheets

Benefits of DDR2 SDRAM compared with DDR1

A major advantage of DDR2 SDRAMs is the higher data rate as well as the lower power dissipation at the reduced supply voltage of 1.8V. The dynamic on-device termination (ODT) improves the signal integrity (SI) in systems that use DDR2 DIMMs or multiple DDR2 SDRAM devices on a single data bus. This results in a significant higher data throughput at lower power dissipation of the signal termination. Besides this, a new additive CAS latency has been intruduced with DDR2 SDRAMs that further improves the read and write performance at higher clock rates.

Block Diagram

Overview

The DDR2 SDRAM Controller LP is a powerful and widely configurable memory controller which provides the user application with access to the high performance DDR2 SDRAMs and DDR2 DIMMs over a simply yet efficient user interface. The proven and flexible architecture of the memory controller is comprised of a high-performance timing state machine that observes all timing requirements of the memory devices and, furthermore, employs advanced techniques to optimize access latencies and data throughput.

The memory controller contains a command queue and a bank management module which minimizes idle times of the internal execution pipeline and enables the continuous execution of read and write requests. Besides this, all low-level tasks such as the periodic refresh and the power-up initialisation sequence are accomplished by the memory controller transparent to the user application.

Features

• High performance DDR2 SDRAM memory access
• CAS latency, burst length and all timing parameters configurable
• command queue architecture for high data throughput through access pipelining
• optimised transaction processing with early activate, hidden precharge and posted read and writes
• full management of all 4 or 8 internal memory banks
• optional multi-ported user interface
• supports self-refresh and power down modes (LP only)
• automatic power-down during idle times (LP only)
• support for 2T clocking scheme (LP only)
• uses ChipSync™ technology in Virtex-5 and Virtex-4 FPGAs
• supports DDR2 SDRAMs from 256 Mbit to 4 Gbit
• available under the terms and conditions of the Xilinx SignOnce license

Applications

• Image processing in industrial, medical and aerospace applications
• Consumer products for SDTV and HDTV markets
• Infrastructure for video broadcasting and networking
• Measurement equipment
• Industrial automation and control

Data Sheets

 DDR2 SDRAM Controller LP for Xilinx FPGAs
 DDR2 SDRAM Controller XS für Xilinx FPGAs