Memory Controller IP Core for DDR SDRAM

Block Diagram
Overview
Features
Data Sheet

Double Data Rate (DDR) SDRAM Memory

Double Data Rate SDRAM provides the designer with a high performance memory for applications requiring high data throughput to a large storage device. The tight timing requirements of the source-synchronous DDR interface imposes additional design complexity that the designer must face during the design implementation. Using the Array Electronics DDR SDRAM Controller, design risks will be reduced considerably enabling the seamless adoption of DDR SDRAM technology.

Block Diagramm

Overview

Array Electronics DDR SDRAM Controller is an innovative and easy-to-integrate core that reduces design complexities and increases design productivity. The memory controller has a robust architecture with a fully pipelined execution model and implements advanced techniques such as overlapped execution of activate and precharge commands leading to an optimal memory transaction processing. This results in the highest data throughput even for the most challenging memory access patterns. For instance, the controller achieves more than 73% of available physical bandwidth for read bursts to randomly distributed addresses.

The core is available for Altera and Xilinx FPGAs and makes use of the DDR related features of a specific target device while preserving an easy implementation flow with minimal timing and implementation constraints. In Xilinx Virtex-5 and Virtex-4 FPGAs, the DDR SDRAM Controller leverages ChipSync™ technology available in the IO structure of these devices to increase the timing margins and ensuring the reliable capture of read data at high clock rates.

Features

• Certified Xilinx AllianceCORE™
• High performance DDR SDRAM memory access
• 73% throughput for random read bursts, 64% for random write bursts (BL=8)
• Supports all JEDEC conform DDR SDRAM devices and DDR DIMMs
• available for all current Altera and Xilinx FPGAs
• supports clock rates of DDR166-DDR400 in Xilinx Virtex-5 and Virtex-4 FPGAs and up to DDR266 in Spartan-3 FPGAs
• Comamnd queue architecture with full management of 4 banks
• highly optimized execution of SDRAM commands using early activate and hidden precharge
• all SDRAM timing parameters configurable
• robust user interface with optional support for a configurable number of user ports
• available under the terms of the SignOnce license

Datasheets

 DDR SDRAM Controller XS for Xilinx FPGAs
 DDR SDRAM Controller XS for Altera FPGAs

Related Documents

DDR SDRAM Controller XS receives Xilinx AllianceCORE product certification.

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