|
|
|
 |
 |
 |
 |
 |
 |
 |
|
3 |
|
FPGA Design |
 |











 | |
|
State-of-the-art RTL design for VHDL and Verilog based design flows
The key features of our digital design offerings are comprised of:
- RTL Coding using VHDL, Verilog or SystemVerilog
- Platform based design using embedded processors
- HW/SW partitioning and interface design
- Deployment of high-speed interfaces
- Verification of RTL design using functional simulation and code coverage
- RTL synthesis and optimisation
- Definition of pinout, floorplan and timing constraints
- Place-and-route and timing closure
- Static timing analysis and gate-level simulation
- Hardware tests
- Documentation and design hand-off
|
|
 |  |
3 |
 |
back |
next |
|
|